incrementing a register

[schoeberl]

Type of issue: feature request

Impact: API addition (no impact on existing code)

Development Phase: proposal

Incrementing a register (a counter) is such a common operation. Maybe we should support an increment operator:

cntReg += 1.U

[johnsbrew]

• such an operator should rather be named :+= to highlight the actual hardware connection taking place behind the scene
• it's fairly easy to provide a naive user-side implementation (scastie) with an implicit class but it raises some interesting discussion.

Discussion

Bindings (Reg, Wire, IO, etc.) are not a first class citizen in Chisel API, only a property of Data (not even reflective from a Chisel-user point of view).

• val b = Reg(UInt()) and val b = Wire(UInt()) share the same type : instances of UInt and cannot be distinguished at compile time
• it is hence not possible to provide a compile time implementation of such :+= operator only for a given Binding
• as the scastie illustrates, when the operator is be implemented on UInt, it can easily allow compilation and elaboration of incorrect circuits (only caught later down the flow, during FIRRTL CheckCombLoops transform)

If the binding was reflexive from chisel-user point of view, it would be at least possible to write a partial implementation, throwing error during chisel elaboration if the underlying Data is not bound to Reg. I am quite in favor to open the binding API as read-only, for example through DataMirror object, in order to provide more reflexivity to end-user and library-developers (without using hacks such as overloading chisel3 package or here using the result of Data.toString)