chisel

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**Type of issue**: feature request **Impact**: API modification **Development Phase**: request **What is the use case for changing the behavior?** When using the shift left/right operator on a `UInt` or...

nullobject

sub field assignment

1

As I cannot reopen issue #878, I created a new one. If this is too hard to implement then we can close it again (maybe with an argument). Subword (individual...

schoeberl

Make Verification Statements (assert,assume) accept printable

10

Fix #2350 ### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x]...

girishpai

Add Sbox in stdlib

7

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you...

ZenithalHourlyRate

[Work in Progress] AXI4 bundle definitions for the standard library

11

Very much work in progress, just collecting some thought for now. Existing implementations: - [riscv-min](https://github.com/ucb-bar/riscv-mini/blob/52904f3b6b459da3d6b95dcbd82c6ef91232f966/src/main/scala/junctions/nasti.scala) - [rocket-chip](https://github.com/chipsalliance/rocket-chip/blob/b36060ebe7bd821ea4b4d1dd2aa9e6d38e7d01b4/src/main/scala/amba/axi4/Bundles.scala) - [chisel-bfm-tester](https://github.com/j-marjanovic/chisel-bfm-tester/blob/0e36f45e7db9a5d2cc94d2d5920aea8c72533537/src/main/scala/bfmtester/AxiIf.scala) - [tensil](https://github.com/tensil-ai/tensil/blob/674184817cbfec868a2489e05f4eea61658a31ba/rtl/src/main/scala/tensil/axi/Master.scala) - [axi-in-chisel](https://github.com/maltanar/axi-in-chisel/blob/789f5153da68ba1d5f46c71e126be8d89c2e76d9/AXIDefs.scala) - [fpga-tidbits](https://github.com/maltanar/fpga-tidbits/blob/a6b4c6ce090e4a2592f62e0c5ccc4ca12766e6ce/src/main/scala/fpgatidbits/interfaces/AXIDefs.scala) - [axi-nodes](https://github.com/yamak/axi-nodes) _this library is...

ekiwi

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [ ]...

sequencer

Discussed in previous dev-meetings: 1. `BitSet.terms` should be an internal API 2. `BitSet` might need have a new binding, supporting bitset operators, we need to use MFC to handle it.(After...

sequencer

**Type of issue**: feature request **Impact**: API addition (no impact on existing code) **Development Phase**: proposal **Other information** **If the current behavior is a bug, please provide the steps to...

debs-sifive

Feature request / proposal. Impact: - much easier for the user to minimize files which cause internal errors so they can be reported to you and - much easier for...

dsw

Exception in thread "main" firrtl.FirrtlInternalException: No width: UnknownType

3

bug report **What is the current behavior?** ``` $ cat input1.firrtl circuit main : module main : node a = dshl(UInt(0), rem(UInt(1), SInt(0))) ``` ``` $ java -cp firrtl.jar firrtl.stage.FirrtlMain...

dsw