chisel

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**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** I am currently working with Chisel 6 and would like to access a module created...

thuako

## About this PR 📦 Updates [com.lihaoyi:os-lib](https://github.com/com-lihaoyi/os-lib) from `0.10.0` to `0.10.3` 📜 [GitHub Release Notes](https://github.com/com-lihaoyi/os-lib/releases/tag/0.10.3) - [Version Diff](https://github.com/com-lihaoyi/os-lib/compare/0.10.0...0.10.3) ## Usage ✅ **Please merge!** I'll automatically update this PR to resolve...

scala-steward

In our build flow, we split the fir elaboration phase and firtool phase into different sandboxes to enable build cache and reproducibility. which means they are not able to observe...

sequencer

UInt<1>(0)' must be a Chisel type, not hardware

2

Hi I defined class cap_result_t , I use this class in another class crevokeModule . then use crevokeModule in another class by this sentence " val crevokeModule = Module(new crevokeModule(new...

mlabaf2

Handle define on views of Probes (backport #4308)

1

Partial fix for https://github.com/chipsalliance/chisel/pull/4291 ### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR?...

mergify[bot]

Firtool error occurs when looking up parameters from a definition of a Module with reset

1

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** This code comes from the [example in the documentation](https://www.chisel-lang.org/docs/cookbooks/hierarchy#how-do-i-look-up-parameters-from-a-definition-if-i-dont-want-to-instantiate-it) and simply use `Module` instead of `RawModule`. ```scala...

unlsycn

Proposal for Verification IR with reset

2

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** Following https://github.com/chipsalliance/chisel/issues/1718, verification IRs are guarded by the reset. However, currently this reset is injected...

poemonsense

Running ``` class misbehavingSVSim extends AnyFreeSpec with Matchers { val parameters = Parameters() val addressMap = AddressMap() "fails SVSim" in { simulate(new myModule(parameters)) { dut => dut.reset.poke(1.B) dut.clock.step() dut.reset.poke(0.B) dut.clock.step()...

HakamAtassi

API for specifying customized transforms in ChiselStage (and dependencies?)

1

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** We have some (lightweight) customized transforms before emitting the FIRRTL. They are still written in...

poemonsense

## About this PR 📦 Updates [org.scoverage:sbt-scoverage](https://github.com/scoverage/sbt-scoverage) from `1.9.3` to `2.1.0` ⚠ 📜 [GitHub Release Notes](https://github.com/scoverage/sbt-scoverage/releases/tag/v2.1.0) - [Version Diff](https://github.com/scoverage/sbt-scoverage/compare/v1.9.3...v2.1.0) ## Usage ✅ **Please merge!** I'll automatically update this PR to...

scala-steward