chisel
chisel copied to clipboard
chipsalliance
Chisel: A Modern Hardware Design Language
Add a Questasim backend to svsim. Add appropriate options to expose it to ChiselSim. Note: this can't be tested unless users/developers have access to Questasim licenses. This if fine, though.
When using Chisel 7.0.0-RC1, IntelliJ displays error messages even though the code compiles successfully. These errors were not present in Chisel 6.7.0 or earlier versions. Specific Errors: 1. `No implicit...
Motivation = Chisel has long lacked a unified and robust approach for exposing metadata. Several prior attempts—such as RocketChip OM/OM2, the Trace API, and the current Property & Class API—have...
warning is generated when the decoder fields chiselType is chiselEnum The warning for example is: ``` [119] [warn] src/main/scala/chisel3/util/experimental/decode/DecoderBundle.scala 88:106: [W001] Casting non-literal UInt to untitl3d.backend.ImmTpe. You can use untitl3d.backend.ImmTpe.safe...
### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...
### Contributor Checklist #### Type of Improvement - Documentation or website-related #### Desired Merge Strategy - Squash #### Release Notes ### Reviewer Checklist (only modified by reviewer) - [x] Did...
As of `firtool` 1.62.0 the format is `--lowering-options=...` #### Type of Improvement Documentation or website-related #### Desired Merge Strategy Squash #### Release Notes ### Reviewer Checklist (only modified by reviewer)...
I can convert a Circuit instance into string FIRRTL code using Serializer.serialize(circuit). So, how can I do the reverse: parse FIRRTL code (or a file) back into a Circuit instance?...
In the "Get me Verilog" section of the FAQ page (the links below), some information might be ambiguous, inaccurate, or outdated. https://github.com/chipsalliance/chisel/blob/main/docs/src/resources/faqs.md#get-me-verilog https://www.chisel-lang.org/docs/resources/faqs#get-me-verilog The FAQ says that the following code...
https://github.com/com-lihaoyi/mill/pull/3347 enables the sandbox for testing by default, and this prevents us from assuming that we are running tests in the workspace root. Instead, we should use the environment variables...
Metadata
Owner
Metadata
Chisel: A Modern Hardware Design Language