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[svsim][chiselsim] Support Questa

1

Add a backend for Questa, in addition to the existing VCS and Verilator backends. Plumb this through to work with ChiselSim.

seldridge

The FIRRTL spec is about to define a `simulation` construct to indicate that a module should be executed as a simulation test. Add a user-facing `SimulationTest` class that can be...

fabianschuiki

In the generated Makefile, the VCS command uses the `-P` option to specify `novas.tab` and `pli.a`, but also uses the `debug_access` option, which can cause conflicts and result in the...

jcvclouds

Hey there! 👋 We've noticed that your Mergify configuration is using some deprecated fields. No worries—we've got your back! This automated PR updates your config to align with the newest...

mergify[bot]

Fix UInt unary negation ScalaDoc (backport #4829)

1

Fixing a ScalaDoc inconsistency noted on Element. Note that unary operators are only allowed to be single characters, `-`, `!`, `~` and `+`, so `unary_-%` has always been invalid to...

chiselbot

ChiselSim not allowing capturing of stdout/stderr

2

ChiselSim should allow for capturing stdout. I'm not sure what is going on here, but something with ChiselSim and svsim is preventing capturing stdout. See the following: ``` scala //>...

seldridge

Mux Tree Generation

4

Hi, I need to constraint the way multiplexer trees are generated. Currently, with Chisel 6.5.0, the following code: ```scala class MuxTree(nBit: Int) extends Module { val io = IO(new Bundle...

escou64

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** ```scala //> using repository "sonatype-s01:snapshots" //> using scala "2.13.16" //> using dep "org.chipsalliance::chisel:7.0.0-M2+618-2ce6ab30-SNAPSHOT" //> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+618-2ce6ab30-SNAPSHOT"...

jackkoenig

[fiirl serializer] Fix for #4791

2

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [X] Did you delete...

tobias1012

Bug in simulation verification

3

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Any Test on windows 10 should recreate this behaviour **What is the current behavior?** The simulator (somewhere)...

tobias1012