OpenLane
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The-OpenROAD-Project
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
I wanted to see how OpenROAD handles very small areas between the perimeter of the core area and placed macros. I took a working design (40um macro halo with the...
### Description Running mpw-5 design repo: https://github.com/antonblanchard/microwatt-mpw5 with openlane tag: https://github.com/The-OpenROAD-Project/OpenLane/releases/tag/2022.04.28_01.44.59. Its failed during`eco_gen_buffer` by not able to find ``` no files matched glob pattern "*_unpadded.lef" while executing "glob -directory...
### Prompt Openlane merges multiple lefs into a single lef to be used in multiple step in the flow. ### Proposal I believe today openroad handles properly reading separate lef...
### Prompt This is how a macro's pdn is defined: ``` define_pdn_grid \ -macro \ -default \ -name macro \ -starts_with POWER \ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)" add_pdn_connect \ -grid macro...
@jjcherry95 pointed out some issues with default SDC file in Openlane, so I thought I'd go through all the timing settings: - `set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]` The comment on this...
### Description Hi, openlane is crashing at the detail routing step, the tool consumes 12GB of memory and crashes, from the final_summary_report.csv looks like the design, only has 7k cells....
### Description Our team encountered syntax error while executing GLS on the verilog file using "FUNCTIONAL" directive in the path OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v in line number 49162. We should be commenting this...
@jjcherry56 points out that Openlane is not constraining the clock tree metal layers. Depending on the process, we might want to use upper/larger metal layers. We need a few changes:...
### Prompt The script `tr_drc_to_klayout_drc.py` used to convert the results to an klayout xml style file is consuming large amounts of memory due to the way it is written. Concretely...
### Prompt low verbosity is nice and all but some steps (detailed routing) has marginally longer runtime than other steps and we can't monitor the progress unless we open the...
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.