netgen topic

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The-OpenROAD-Project

An open-source static random access memory (SRAM) compiler.

VLSIDA

Minimal SKY130 example with self-checking LVS, DRC, and PEX

sgherbst

Massively Parallel Simulator of Optical Coherence Tomography (OCT-MPS)

SiavashMT

JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.

iic-jku

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware us...

vsdip