openram topic

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The-OpenROAD-Project

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

google

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

efabless

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

efabless

Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

ShonTaware