Mike Thompson

icon indicating a website link http://www.openhwgroup.org icon indicating an email [email protected]

icon company @openhwgroup icon location Ottawa, Ontario, Canada icon location Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.

Results 646 comments of Mike Thompson

Error writing to memory using test bench files located in cv32e40s/tb/core

Thanks for your interest in the CV32E40S @MBleaux. The "core" testbench for CV32E40S is not supported at this time. We would gladly accept a pull-request to restore it. Please start...

Error writing to memory using test bench files located in cv32e40s/tb/core

> I couldn't find in the manual how to model these signals. As you already know, the specification for the OBI is [here](https://github.com/openhwgroup/obi). According to the CV32E40S User Manual, you...

How can I use Spike ISS?

> does this IP create any assembly files temporarily and where does it keep? As explained in the README, the testbench for this core is in the [CORE-V-VERIF](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/dev) repo (cv32e40p/dev...

Fix: Handle underflow properly at subnormal/normal boundary

Hi @IhsaneTahir. Typically we do not include patch files to PR as they are redundant once the merge is done. Is there a reason the patch file is needed? If...

Fix: Handle underflow properly at subnormal/normal boundary

Hmmm. That workflow is not documented herein (at least, I didn't find it), and it is not the way most other OpenHW are maintained. Having said that, if that what...

Quartus standard/free version compatible CV32 core - available now

Hi @svenka3, thanks for your interest in OpenHW and the CV32E40P. In general, the OpenHW Foundation's projects target Industrial and Research Institute users, not hobbyists. At least two of the...