Mike Thompson

Hi @algrobman. As a long-time user of riscv-dv, I agree with you. Generally speaking, in functional verification of RTL models (which is largely what OpenHW use riscv-dv for) test efficiency...

Sounds like a regression management issue to me. Send me and email (available on my GitHub profile) if you'd like to discuss.

FWIW, I think you are right @kaddkaka. Maybe try `bit_difference = temp.count('1')`?

Hi @khandelwaltanuj, can you mention the GitHub pull-request that resolved this issue? Thanks.

Hi @lining2020x, thanks for your interest in CORE-V-VERIF and this pull-request. In order for us to accept it, you must sign the Eclipse Contributor Agreement. Please see [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md) for the...

Hi @XavierAubert, thanks for this issue, your careful analysis and especially for your example (steps to reproduce). I agree with your strategy to not increase this timeout value and keep...

Hi @Spoorthi102003, thanks for our interest in the CV32E40X. Unfortunately, Verilator has never been able to compile the CV32E40X RTL because it contains SystemVerilog interfaces. So we have not put...

> I have just removed the commented code. And I believe that user can define its own method in the derived class. You are right, that will work. By "work"...

> or I can have just empty virtual function ... Great idea! Please add a UVM warning to indicate that it should be implemented.

> One option is I just update the READ saying response handler is disabled by default and not do anything else. I like this option. I assume enabling the response...