Mike Thompson

Thanks for this Issue @LucaRufer. Just to clarify, are you seeing incorrect _behaviour_ or unnecessary offload requests that (eventually) lead to correct behaviour?

> So it seems it only causes unnecessary offload requests without incorrect behaviour. Well, _that's_ a relief. Nevertheless, this is clearly not desirable for power dissipation. We'll look into it....

Hi @vinomutty, thanks for your interest in CORE-V-VERIF! Without more information it is difficult to say for certain what the trouble is. In the future, when creating an Issue, please...

Hi @vinomutty, we haven't heard from you in a more than a month, so I will assume either my suggestions on #2539 resolved your issue or you are no longer...

Hi @AyoubJalali. This should now be resolved now that @2549 is merged in. If you are happy with it, let me know and I will close this issue.

Hi @ahmd-kamel, thanks for your interest in the CV32E40P. For the latest version of this core (v1.8.3), you can find the list of waived lint warnings in Issue #670. Note...

The last time I attempted to use Verilator with the E40X it would not compile. The E40X RTL incorporates SystemVerilog Interfaces and at the time Verilator did not support them....

There are two problems here: 1. You are using Verilator. As both @silabs-robin and I have indicated, it is very unlikely that Verilator can compile the E40X. 2. Because of...

It is doubtful that the `vsim.mk` file is fullly up-to-date. Also, please ensure that you are using a fully featured version of Questa.

Hi @vinomutty, this Issue seems to be the same one as #2537. If that is the case, please close that Issue and we will continue the discussion here. A couple...