Mike Thompson

icon indicating a website link http://www.openhwgroup.org icon indicating an email [email protected]

icon company @openhwgroup icon location Ottawa, Ontario, Canada icon location Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.

Results 646 comments of Mike Thompson

FDIV FSQRT Rounding Mode Calculation Mismatches

Thanks for reporting this @M31581, it is very much appreciated. As you may know `cvfpu` is under-going verification as part of the [CV32E40Pv2](https://github.com/openhwgroup/programs/blob/master/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md) project. At this time cvfpu is not...

Create and integrate sleep unit

Hi @davideschiavone. One the CVE2 project (Kanban) board, the status of this task is "In Progress", but this task does not reference any associated PR. Is PR #121 the one...

Create and integrate sleep unit

@cairo-caplan has indicated that this feature implemented as part of https://github.com/openhwgroup/cve2/pull/122 and https://github.com/openhwgroup/cve2/pull/131. It is implemented on the body of the code of cve2_top.sv, as shown below, instead of a...

Update Makefile(s) to support Cadence Xcelium and other TBD simulators

The current head of the `cv32e20/dev` branch of core-v-verif (969d2d7) is working with Xcelium. The following works as expected: ``` $ make test TEST=hello-world SIMULATOR=xrun USE_ISS=0 ``` What other simulators...

Update Makefile(s) to support Cadence Xcelium and other TBD simulators

[CORE-V-VERIF Pull-Request #2195](https://github.com/openhwgroup/core-v-verif/pull/2195) adds support for VCS.

Update Makefile(s) to support Cadence Xcelium and other TBD simulators

As far as I can tell, the Makefiles for CV32E20 have supported Questasim (VSIM) as of [CORE-V-VERIF Pull-Request #2003](https://github.com/openhwgroup/core-v-verif/pull/2003). In any case, I can report that a `ci_check` regression runs...

Floating-Point Performance Bug for FPU_*_LAT>1

Hi @jenniferhellar and @pascalgouedo. To Jennifer's points: 1. I would recommend making this clarification in the `Cycle Counts per Instruction Type` table in the [pipeline](https://github.com/openhwgroup/cv32e40p/blob/360d272898d81806be3377193870dbf83a3ea79f/docs/source/pipeline.rst?plain=1#L146) chapter. Knowing what I know...

Floating-Point Performance Bug for FPU_*_LAT>1

> I could think about it and propose something during my spare time. Gracias mi amigo!

Bug : MTVAL is not read-only zero

The [CVA3265X User Manual](https://docs.openhwgroup.org/projects/cva6-user-manual/06_cv32a65x_riscv/index.html#_machine_trap_value_mtval_register) states that the mtval register is an MXLEN-bit read-only 0 register, so I think the RTL is doing the right thing. This is yet-another Spike configuration...

Add capability to tp_translator to automatically determine value of CV_DV_UTILS_DIR.

> The example that yu have pointed to is of a makefile but we are not using makefile to compile cv_dv_utils. Yes, that is true, but a Python script can...