Mike Thompson

Can you provide me with the _exact_ set of command-lines you ran to obtain this? Please start with `git clone...`

Hi @jason23g, thanks for your question. I suspect you are asking about the _lack_ of a file `core-v-verif/vendor/riscv/riscv-isa-sim/riscv/insns/c_ld.h`. Is that correct? If so, I suspect the answer is that currently,...

> Ok could you guide me on how to add c_ld in the current implemantation of core-v-verif ? Oh, I _love_ to be able to do that. Unfortunately, no such...

Hi @SOUMYADIPSAHA10 and @saiburra93, there are no waveforms to see. `riscv-dv` does all its work without consuming any simulation time.

The original assignee is no longer with the project, so am assigning it to @MarioOpenHWGroup (who is already working on it).

Hi @nimakolahi, it seems you have found a path forward. As you have seen, the RVFI Tracer used by this core requires a SystemVerilog simulator capable of supporting UVM such...

Hi @Northeus, thanks for your interest in OpenHW. I see that there is a new version of DSim Desktop (20240923.0.0 on 2024-10.25). I am using 20240923.0.0 from 2024-09-25, so it...

It seems there are two problems here: 1. DSim does not appear to handle some SVA code constructs properly. I have found a work-around for this. 2. The DSim Makefile...

Hi @vinomutty. You've got two problems here with the same root-cause. That is, the so-called "core" testbench does not attract a lot of attention and so it tends to suffer...

I would recommend the latest version, `9d9cae78b01a11458953133d1173c61933a2ba86`. You do not need to clone the RTL yourself. The Makefiles will automatically clone a specific version of the RTL from the CV32E40S...