Flatten top level output structs when rending VHDL - most tools dont allow complex types at the top level

[JulianKemmerer]

Just flatten one level - so typical output_t wrapper structs can naturally look like multiple ports in the VHDL

Maybe can make a pragma to not always do?

Related to using global variables as ports: https://github.com/JulianKemmerer/PipelineC/issues/123

Thanks Bartus!

typedef struct my_struct{
uint_1t a;
uint_1t b;
} my_struct_t ;

my_struct_t my_fun(void) {
  my_struct_t temp;
  temp.a = 0;
  temp.b = 0;
  return temp;
}

entity module is
port:
my_struct_t_a : out std_logic;
my_struct_t_b : out std_logic;