Tingyuan LIANG

A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

zslwyuan

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...

zslwyuan

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

zslwyuan

Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

zslwyuan

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

zslwyuan

In this work, we use convex optimization package in MATLAB to implement multi-user transmit beamforming problem and linear regression. This is the homework 2 of ELEC 5470 Convex Optimization, HKUST.

zslwyuan

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

zslwyuan

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print...

zslwyuan