Tingyuan LIANG

Excellent work!!!! It could be very practical for HLS application!!! I do hope this project can benefit more designers!! I have gone through a similar development flow of an HLS...

Hi @eminghuliev , Thanks a lot for your suggestion! Yes! You are right! Using look-ahead adder will definitely improve the performance! Just need to carefully handle the compatibility among different...

Sorry for replying late but I am not sure about your issue. Maybe there is some useful information in "C:/Users/Ren.Ps/Documents/VHDL/SIMD/SIMD.sim/sim_1/behav/xsim/elaborate.log"? For your second issue, I guess that the SDF file...

> Oh,I had the same problems when I ran simulation.And it`s also in Xilinx Vivado 2020.1 version. Hi @jimik7 , can you provide the log file so I can have...

> Interesting. What happens when you try to boot Linux in spike with -p16. Does that work? @jerryz123 Thanks, Jerry! I think I found the cause. It seems that the...

@jerryz123 It is interesting. According to the config information shown in the kernel code (line 287: range 2 32), does it means that RISC-V system cannot support hardware with more...

@michael-etzkorn actually we are running the design on a larger FPGA but go through a similar prototyping flow. ^_^

> @zslwyuan Could you please show a complete updated prologue.tcl? thanks. I'm experiencing the same issue. Hi @wangliwei-intel check the following codes to update prologue.tcl: ``` # See LICENSE for...

It seems that your repo missed some components, try to follow the instruction in the documentation to initialize your repo: https://chipyard.readthedocs.io/en/latest/Chipyard-Basics/Initial-Repo-Setup.html#setting-up-the-chipyard-repo the downloaded things are the dependency libs declared in...

modularize the PlacementInfo since it contains too much information and is shared by too many modules in the placer.