ddr topic

DDR2 memory controller written in Verilog

adibis

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

PrimeMHD

CoreFreq : CPU monitoring and tuning software designed for 64-bit processors.

cyring

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

RC4ML

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

splinedrive

DDAL(Distributed Data Access Layer) is a simple solution to access database shard.

hellojavaer

u-boot DDR mods ~

3F

The Bug Reporting Repository for OutFox LTS 0.4, Alpha V and Steam Early Access Builds

TeamRizu

Xilinx PCIe to MIG DDR4 example designs and custom part data files

d953i

SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus

1a2m3