Zbigniew Chamski

### Is there an existing CVA6 bug for this? - [X] I have searched the existing bug issues ### Bug Description Issue identified when validating PR #945 by means of...

This PR adds the CVA6-side support for VCD and FST dump generation using Verilator. It has a companion PR on `core-v-verif` (branch `cva6/dev`) that provides the unified trace control for...

This PR adds the upward propagation of address, mask and data of memory operations from the LOAD/STORE unit level to the RVFI tracer. The address and data information is required...

# Purpose Improve usability of VPTOOL, for now on CVA6 verification plans: * [generic] Print all elements of a verification item in human-readable form, including the lists of applicable cores;...

Add unified tracking of simulator elaboration and simulation performance

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Add a means of tracking the performance of simulators used in verification, both in terms of model elaboration/compilation time, and of simulation time proper. The collected performance data are added...

Generate separate per-target logs when simulating.

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* verif/sim/Makefile (veri-testharness): Don't add target name to waveform file name. (vcs-uvm): Ditto. * verif/sim/cva6.py (run_assembly): Add target name to log file name. (run_elf): Ditto. (run_c): Ditto. (iss_sim): Ditto. (iss_cmp):...

Improve environment setup. Fix Verilator installation process.

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* verif/sim/setup-env.sh: Double-quote variable values. Install Verilator in 'tools/verilator' by default. Add SPIKE_PATH to PATH. * verif/regress/install-verilator.sh: By default use per-version dirs to build and install Verilator. Add and improve...

[TASK] Compare Spike and RTL in tandem

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**Background** Lockstep ("tandem") co-simulation allows early detection of divergences between behaviors of different simulation models on the same test case. Typically, an Instruction Set Simulator (ISS) and an RTL simulator...

[TASK] Modify Spike to match core-specific configuration

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**Background** Spike implements a complete set of functionality corresponding to the RISC-V specifications. At times this set can be a superset of features of an implementation, in particular in the...

[TASK] Add CSRs and MEM read info to CVA6 RVFI

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**Background** CSR state information (either full state or change sets) is necessary to verify the RTL behavior against the Reference Model (the Spike ISS). In mainline Spike the CSR state...