[BUG] CV32A6 incorrectly decodes compressed FP loads (and probably stores)

[zchamski]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

Issue identified when validating PR #945 by means of unit tests introduced in https://github.com/openhwgroup/core-v-verif/pull/1392:

• Test of instruction C.FLD on RV64GC passes (RTL traces from VCS and Verilator match the Spike trace)
• Test of instruction C.FLW on RV32IMAFC fails:
  • Both RTL traces (from VCS and from Verilator) differ from the Spike trace
  • The two RTL traces are identical.

Analysis

• The RTL execution hits an illegal instruction exception at the PC of instruction C.FLW fs0, 0(s1)
• The RTL execution log contains incorrent disassembly (see PR https://github.com/openhwgroup/core-v-verif/pull/1418) but the RTL control flow does match the Spike-side all the way up to the exception.
• waveform analysis points to the instruction decoder (core/decoder.sv) which raises the ILLEGAL_INSTRUCTION exception upon detecting a request to perform a 64b FP load in the decompressed instruction.

Root cause

• The compressed instruction sets of RV32C and RV64C differ on several instructions in all three compressed quadrants.
• The compressed decoder handles the differences in instruction meaning in quadrant 1 (opcode[1:0] == 2'b01) of the compressed instruction space, but not in quadrant 0 (opcode[1:0] == 2'b00) nor quadrant 2 (opcode[1:0] == 2'b10).

Proposed fix

Rewrite the "dual-personality" entries of the compressed decoder so that they apply the correct decompression scheme according to the current XLEN.