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Published 20 hours ago • verified publisher icon veripool

Misalignment of labeled assertions inside if...else...

Open veripoolbot opened this issue 9 years ago • 1 comments

Author Name: Bernd Beuster Original Redmine Issue: 988 from https://www.veripool.org

verilog-version 2015-09-21-d3012e9-vpo

veripoolbot avatar Oct 30 '15 10:10 veripoolbot

Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-11-19T13:28:46Z

Still a problem, perhaps someone would like to contribute a patch?

veripoolbot avatar Nov 19 '17 13:11 veripoolbot