verilog-mode
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veripool
bus width alignment
Author Name: Alex Hornung Original Redmine Issue: 562 from https://www.veripool.org Original Date: 2012-09-12
I've started using verilog-mode a few months ago and am overall quite happy with it. However there is one thing I'm really missing: alignment of the bus widths (or rather of the square brackets and colons).
I (amongst others) like to format things as follows:
reg [DATA_WIDTH-1:0] foo;
reg [ 4:0] bar;
reg [ FOO_WIDTH-1:0] baz;
wire [ 1:0] bla;
wire [ 15:0] bla2;
Is there a way to tell verilog-mode to do that automatically, similarly to how it aligns the names (foo, bar, baz, bla)? If not, would it be possible to add that?
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2012-09-12T18:18:19Z
Not presently. Alas as we have a backlog for bugs on the existing styles you'll probably need to implement it yourself. If you can make a patch we'd certainly be willing to take it back.
Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2013-05-22T02:11:49Z
BTW to find the logic around this in the sources, look for verilog-auto-lineup. I would suggest adding an additional case to that variable to support this.
Original Redmine Comment Author Name: Vasiliy Zukanov Original Date: 2013-06-27T19:51:41Z
I'll try to do it. It is clear from the example how one-dimensional vectors' declarations should be indented. However, it is not clear to me what approach should be taken in general. Can someone propose indentation styling for the following declarations:
wire [7:0] one_dim;
reg [WIDTH-1:0][BIT_WIDTH-1:0] two_dim;
logic [`MAX_W-1:0][3:0][7:0] tree_dim
Original Redmine Comment Author Name: Alex Hornung Original Date: 2013-06-28T08:09:28Z
I've had a shot at implementing it in a slightly different way which seems slightly more popular, but didn't get very far with emacs lisp:
reg [DATA_WIDTH-1:0] foo;
reg [4:0] bar;
reg [FOO_WIDTH-1:0] baz;
wire [1:0] bla;
wire [15:0] bla2;
This style, however, would also work well with multiple packed dimensions,
wire [7:0] one_dim;
reg [WIDTH-1:0][BIT_WIDTH-1:0] two_dim;
logic [`MAX_W-1:0][3:0][7:0] tree_dim;
So I think it's the better way of doing it - simply right-aligning the packed dimensions, and padding the start of the longest packed dimension description so that it starts after the longest type (logic being the longest type, while the middle one has the longest packed dimension description).