Understand few defconsts

[veripoolbot]

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Author Name: Kaushal Modi Original Redmine Issue: 1160 from https://www.veripool.org

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Hi,

I was working on refactoring @verilog-prettify-expr@ function and I came across the @verilog-basic-complete-re@ and @verilog-complete-reg@ variables.

These are @defconst@ variables but they are lacking docstrings. So just looking at their values, I cannot tell what they mean..

Also, for consistency, should @verilog-complete-reg@ have been named @verilog-complete-re@?

Looking at @verilog-basic-complete-re@:

(defconst verilog-basic-complete-re
  (eval-when-compile
     (verilog-regexp-words
      `(
        "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
        "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
        "if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
        ))))

At first glance, this seems to be a regexp for procedural blocks, but then it does not contain @final@ (IEEE 1800-2012 Section 9.2). Then it has @module@, but no @class@. So I couldn't correlate this set of keywords with any given set in the standard.

• Do we need to add more keywords to this regexp?
• A docstring will help tremendously.

[veripoolbot]

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Original Redmine Comment Author Name: Wilson Snyder (@wsnyder) Original Date: 2017-05-08T23:53:46Z

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I can't personally advise as its not my code, but welcome a patch to improve the docs after you figure it out!