vtr-verilog-to-routing
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Verilog to Routing -- Open Source CAD Flow for FPGA Research
Moving from email to GitHub feature request. #### Proposed Behaviour Provide support for simple dual port (SDP) RAMs in ODIN/ODIN+Yosys ![memory_ports](https://user-images.githubusercontent.com/35443216/184049245-d8963197-12cc-4644-8c2b-6e4f7fa1a904.png) #### Current Behaviour Currently, only single port (SP) and...
#### Description Changed remaining malloc/calloc/reallocs to new. #### How Has This Been Tested? Passes all CI tests. #### Types of changes - [ X] Bug fix (change which fixes an...
#### Expected Behaviour The resource usage between the two flows should be similar. #### Current Behaviour For the CLSTM benchmark, we are seeing the resource usage differ greatly when we...
WIP will write this later, just need to check documentation. Do not merge
./vtr_flow/scripts/qor_compare.py doesn't work on parse_results files from GitHub artifacts without editing the parse_results file. ./vtr_flow/scripts/qor_compare.py requires QoR metrics in .txt files to be seperated by a tab ONLY (i.e. \t),...
This PR provides the initial support for the SystemVerilog and UHDM plugins designed for Yosys. The Surelog and Yosys-F4PGA-Plugins repositories are added as submodules to the VTR repository. Both Surelog...
Added a number of routing algorithms that can be used to route traffic flows within the NoC during placement. #### Description - Added a base general routing class called NocRouting...
## Description In this PR `rr_graph_reader` and `rr_graph_writer` from vpr/src/route are moved to librrgraph. We also avoid dependencies from vpr and try moving the vpr dependencies to the according libraries....
Initial placement used to fail in case of high utilization or long chains. New approach called dense_placement has been added to initial placement, make it possible to redo initial placement...
This allows vpr to be built on M1 MacBooks #### Description For this to work, you need `tbb@2020` from Homebrew. I was able to build the software using this CMake...