vtr-verilog-to-routing
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verilog-to-routing
Support for simple dual port RAMs in ODIN/ODIN+Yosys
Moving from email to GitHub feature request.
Proposed Behaviour
Provide support for simple dual port (SDP) RAMs in ODIN/ODIN+Yosys
Current Behaviour
Currently, only single port (SP) and true dual port (TDP) RAMs are supported:
* en2 *
* en1 | * en
* CLK | | * CLK |
* __|_____|_____|___ * __|_________|_____
* | | * | |
* | | * | |
* data1 --->| | <--- addr1 * | |
* | DPRAM | * data --->| SPRAM |<--- addr
* data2 --->| |<--- addr2 * | |
* | | * | |
* |________________| * |_________________|
* | | * |
* | | * |
* v v * v
* out1 out2 * out
Possible Solution
Context
This is not needed right now. This is for the future. Adding Dr. Kenneth Kent to assign it to a future student.
FYI - Yosys recently went through a pretty big refactor to support more types of memory styles. See the work from @mwkmwkmwk - https://github.com/YosysHQ/yosys/pulls?q=author%3Amwkmwkmwk+
@poname - considering the Yosys recent changes on memory blocks, you would be required to consider upstreaming the VTR-Yosys for Odintechmap and provide the support for newly added components, as well. This could be postponed to the second phase of your development as we expect Odintechmap initially work fine with the old version of Yosys added to the VTR repository. Adding @vaughnbetz on this thread as he already requested for upstreaming VTR-Yosys.
