vlsi-physical-design topic
OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
DREAMPlace
Deep learning toolkit-enabled VLSI placement
dr-cu
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
salt
Steiner Shallow-Light Tree for VLSI Routing
Physical-Design-with-OpenLANE-using-SKY130-PDK
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII F...
Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Parser-Verilog
A Standalone Structural Verilog Parser
magic_vlsi_examples
Some simple examples for the Magic VLSI physical chip layout tool.
RDF-2019
DATC RDF