vlsi-physical-design topic

A High-performance Timing Analysis Tool for VLSI Systems

OpenTimer

Deep learning toolkit-enabled VLSI placement

limbo018

Dr. CU, VLSI Detailed Routing Tool Developed by CUHK

cuhk-eda

Standard Cell Library based Memory Compiler using FF/Latch cells

AUCOHL

Steiner Shallow-Light Tree for VLSI Routing

chengengjie

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII F...

shariethernet

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

OpenTimer

A Standalone Structural Verilog Parser

OpenTimer

Some simple examples for the Magic VLSI physical chip layout tool.

andrsmllr

DATC RDF

ieee-ceda-datc