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Published 20 hours ago • verified publisher icon SystemRDL
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Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Documentation Status build Coverage Status PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

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verified publisher icon SystemRDL

Metadata

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

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