rv32i topic

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

syntacore

A self-hosting and educational C optimizing compiler

sysprog21

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

darklife

RISC-V CPU Core (RV32IM)

ultraembedded

32-bit Superscalar RISC-V CPU

ultraembedded

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

WangXuan95

Small Processing Unit 32: A compact RV32I CPU written in Verilog

maikmerten

RISC-V RV32I[MA] emulator with ELF support

sysprog21

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

stnolting

RISC-V Software Simulation

kamiyaowl