axi4-lite topic
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
core_usb_host
Basic USB 1.1 Host Controller for small FPGAs
axi4-interface
AXI4 and AXI4-Lite interface definitions
axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
core_audio
Audio controller (I2S, SPDIF, DAC)
core_usb_bridge
USB -> AXI Debug Bridge
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
AMBA-AXI4-Lite
Master and Slave made using AMBA AXI4 Lite protocol.
NoCpad
HLS for Networks-on-Chip