asic topic

A collection of great digital IC project/tutorial/website etc..

qninth

A place to keep my synthesizable verilog examples.

JeffDeCola

A simplified and standardized interface for Bitcoin ASICs.

UpstreamData

Control and status register code generator toolchain

SystemRDL

Generate address space documentation HTML from compiled SystemRDL input

SystemRDL

Import and export IP-XACT XML register models

SystemRDL

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

SystemRDL

Generate UVM register model from compiled SystemRDL input

SystemRDL

Some simple examples for the Magic VLSI physical chip layout tool.

andrsmllr

Tool to fetch and parse data about Efabless MPW projects

mattvenn