asic topic

HW Design: A Functional Approach

bogdanvuk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

google

32-bit Superscalar RISC-V CPU

ultraembedded

Awesome ASIC design verification

troyguo

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Juniper

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

zssloth

SystemRDL 2.0 language compiler front-end

SystemRDL

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

pulp-platform

Hive OS client for ASICs

minershive

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

google