asic topic

A 256-RISC-V-core system with low-latency access into shared L1 memory.

pulp-platform

Custom chips reverse-engineered from silicon

furrtek

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called proce...

trilomix

Mining Pools Made Easy. ⛏ 📦 🏆

hashrabbit

A seamless python to Cadence Virtuoso Skill interface

unihd-cag

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperat...

lakshmi-sathi

Start a Mining Pool, Software, Script to Install, Configure & Setup Yiimp/Miningcore/NOMP Crypto Mining Pool on Ubuntu 16.04, 18.04, 20.01, 20.04, 21.01, 21.04, 22.04 VPS or Dedicated Servers

goodthebest

FPGA CryptoNight V7 Minner

lulinchen

Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs

ulixxe

Control and Status Register map generator for HDL projects

esynr3z