asic-design topic

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

dpretet

KiCad symbol library for sky130 and gf180mcu PDKs

lethalbit

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has...

abdelazeem201

IC implementation of Systolic Array for TPU

abdelazeem201

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

KastnerRG

Quasar 2.0: Chisel equivalent of SweRV-EL2

Lampro-Mellon

Convolutional accelerator kernel, target ASIC & FPGA

lirui-shanghaitech

hardware design of universal NPU(CNN accelerator) for various convolution neural network

thousrm

RISCV CPU implementation in SystemVerilog

dpretet