axi-stream topic

High throughput JPEG decoder in Verilog for FPGA

ultraembedded

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G...

alknvl

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

KastnerRG

UART to AXI Stream interface written in VHDL

fcayci