Jiuyang Liu
Jiuyang Liu
RISC-V Debug Spec 1.0 has released for almost one years, It's reasonable to upgrade Rocket-Chip DM and Rocket Core to complain with 1.0 **Type of issue**: feature request **Impact**: API...
Most of configurations in RC is untested. Making RC almost impossible to accept RTL changes to new RV extension from community. 0. Currently Makefile-based testing decoupled Chisel elaboration, FIRRTL lowering,...
RocketChip should be added some documentations to unify the code style: **Type of issue**: feature request **Impact**: no functional change **Development Phase**: proposal **Other information** https://github.com/chipsalliance/rocket-chip/issues/255 **What is the use...
This is needed for RC bumping after chipsalliance/rocket-chip#2967 get merged.
In the bus protocol expecting. There is a case that we only need to expecting a part of signals. For example: To test TileLink protocol, I'm expecting a 128-bit width...
Since tester2 only has cycle-based simulator interface, async multi-clock seems not be possible. But main clock can be supported, after #156, we can set clock by annotation, and let user...
I notice there will be a case that multiple assertion will be raised in one cycle, do I need to collect them together and throw them, but I notice scalatest...
If firrtl transform altered the top IO like https://github.com/sequencer/diplomatictester does. The removed IO will still be elaborated to verilator API. since the IOs are set by https://github.com/ucb-bar/chisel-testers2/blob/db85e6fcb5ce2d8397ea0d9ed1745cdd5b7b9e35/src/main/scala/chiseltest/legacy/backends/verilator/Utils.scala#L35 This will help...
In treadle, we have `ScalaBlackBox` for circuit behavior model. However this behavior model can only be executed by treadle but no verilator/vcs. In the verilog verification, We cannot use treadle....
This is a WIP work. It allows FIRRTL directly emit MLIR without parsing by MFC. ### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? -...