Power domains representation

[jwright6323]

Dumping a conversation with @colinschmidt. This is basically my vision for how the library-level hammer IR will interact with the internal power domain representations.

I think that is related to the library-level CPF stuff where libraries say what they need rather than a top-down approach e.g. the std cell lib might say “I have 4 pins”

• VDD primary power that can go 0.6-0.9V
• VSS primary ground
• VPP body power that must be connected externally, range 0.6-0.9V
• VSS body ground that must be connected externally (edited) and by default hammer would read this info and say “OK I need to make 4 nets, and my default behavior will be to tie VPP to VDD*” (edited) and then at the design level you’d say “Module A has power domain VDDA, level 0.8V (modes we’ll handle later)” “Module B has power domain VDDB, level 0.8V” etc so that would by default create nets:
• VDDA
• VDDB
• VPPA
• VPPB
• VSS
• VBB (edited) then let’s say you had an analog widget inside Module A with two supplies, VDDDIG and VDDANA you might describe these in the IR like so:
• VDDDIG - primary power supply, 0.6V - 0.9V, digital (maybe the std cells also have the “digital” property”)
• VDDANA - primary power supply, 0.8V, analog, isolate

[edwardcwang]

This generally sounds good. Might be good to still be able to have an escape hatch or other mechanism where users can arbitrarily designate power nets/domains top-down that can interoperate with this scheme.

[jwright6323]

That is what @colinschmidt is currently working on- this is more of a future vision, and one that may not even come to pass.

[sequencer]

I noticed that https://github.com/ucb-bar/hammer/blob/64675e473d3de4edf77ef31d4c90045b956de3a2/src/hammer-vlsi/hammer_vlsi/hammer_vlsi_impl.py#L1297 implicitly assume that entire chip has only one voltage, I wonder If I wanna give a multi power domain design, what should I supposed to do?

[jwright6323]

@sequencer I believe it currently does support multiple domains, but they all have to have the same nominal voltage (but they can be different on the real chip if you insert level shifters). You could either fix this python code and submit a PR, or you could use a manual CPF.

[sequencer]

Got it I’ll compose a PR latter in this week.