Rishiyur S. Nikhil

Just observed that this "internal error" bug still exists, with this version: Verilator 5.005 devel rev v5.004-63-g46cc7b5d0 As it happens I tried it on the same files as the original...

I don't know the state of maintenance of RISCY-OOO in the MIT repo but, FYI, you can get a working version of RISCY-OOO at: https://github.com/bluespec/Toooba This version has some improvements...

Dear Polypolen (apologies, I don't know your real name), [ Apologies for delays in responses; I'm juggling 4-5 projects, so I get back to this one only periodically. ] I...

You are correct, Forvis is not yet properly handling dynamic changes to WARL fields such as MISA.MXL, MSTATUS.SXL and MSTATUS.UXL. These are still on my TODO list (marked as such...

All the RV32 and RV64 tests found in the repo, at: Test_Programs/riscv-tests/isa/ are copied as-is from the following flow: $ git clone https://github.com/riscv/riscv-tools.git ... follow the directions in riscv-tools/README, ......

> For writes, that doesn't quite work because of the requirement for the write value to be calculated after `mem_write_ea()` but before `mem_write_value()`. Why? Can’t the write-value calculation (just a...

>. I thought that side effects on reads to CSRs were forbidden (explicitly) in the spec. In addition to the text cited by @Timmmm there is also this text, in...

The question is, what should the Sail model do? I think the current definition of physical addrs as 32 bits for RV32 is not correct. With the 32 bit setting,...

@allenjbaum I think you're discussing different points than the issue I am raising. You're discussing the various ISA nuances of Sv32 translation (when it occurs, how it occurs, …), which...

> Tbh I think we should probably try to fully use Sail's fancy type system in this new > VM code rather than just expanding everything to 64 bits immediately....