Rishiyur S. Nikhil

Results 3 issues of Rishiyur S. Nikhil

'mem_read_priv()' [riscv_mem.sail, L180] declares the address argument as 'xlenbits' But Sv32 phys mem addrs are 34 bits, not 32 (XLEN) bits. If RV32 is configured WITHOUT Sv32, are phys addrs...

bug

This first comment just describes the issue(s). Follow-up comments discuss possible solutions. Currently the Sail model writes out a log file in ASCII format. Issues: * Logs can become very...

Here are some suggestions to improve the text in: Version 1.0.0-rc3, Revised 2024-05-15: Frozen https://github.com/riscv/riscv-debug-spec/releases/download/1.0.0-rc3/riscv-debug-specification.pdf * Sec 1.2 Context: Should 'Zicsr' be included in this list? * Sec 3.7.1.3 Access...