Rishiyur S. Nikhil

Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document

rsnikhil

Bluespec BSV HLHDL tutorial

rsnikhil

Formal specification of RISC-V Instruction Set

rsnikhil

Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference

rsnikhil

A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)

rsnikhil

Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)

rsnikhil

Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

rsnikhil