Rishiyur S. Nikhil
Rishiyur S. Nikhil
In next week's 'tech-golden-model' group meeting, there will be a presentation on exactly this topic by someone who has been working for some time on a JIT compiler for the...
I'd imagine compiling to full SystemVerilog, for simulation only, should not be too difficult; it would likely be difficult to compile to **synthesizable** SV?
I have some code that may be useful in implementing gdb control of the Sail simulator (open-source, Apache license): https://github.com/bluespec/RISCV_gdbstub At Bluespec, Inc., we use this for GDB control of...