Rishiyur S. Nikhil

In next week's 'tech-golden-model' group meeting, there will be a presentation on exactly this topic by someone who has been working for some time on a JIT compiler for the...

I'd imagine compiling to full SystemVerilog, for simulation only, should not be too difficult; it would likely be difficult to compile to **synthesizable** SV?

I have some code that may be useful in implementing gdb control of the Sail simulator (open-source, Apache license): https://github.com/bluespec/RISCV_gdbstub At Bluespec, Inc., we use this for GDB control of...

I have looked at 4 public RISC-V specifications for "trace/log", and none of them seem suitable for a full trace output from the Sail model. I recommend the Sail model...

Bluespec, Inc. has defined a trace model (PDF attached) which could be used by the Sail model. Bluespec, Inc. is ready to contribute this spec to RVI as an open...

Bluespec, Inc. is also happy to contribute to RVI a C program (which already exists) which reads and parses the binary trace and prints it in human-readable format. This could...

Thanks for the link for TestRIG's RVFI spec (I had not seen that before). > That's certainly not true for RVFI as we implement it You're right. In RVFI, a...

> We parse RVFI packets and print them in though that's in Haskell (I like that! but) I think the Sail model audience's preference for such a reader is likely...

Question re. Sec 3.14.2 Debug Module Control (dmcontrol, at 0x10) > On any given write, a debugger may only write 1 to at most one of > the following bits:...

On HALTREQ, the halt actions update DPC, DCSR.CAUSE, DCSR.PRV, DCSR.V. What if current instruction (at which we halt) happens to be a CSRRxx instruction that writes DPC or DCSR? What...