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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
*** Running vivado with args -log vlsu.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vlsu.tcl ****** Vivado v2018.1 (64-bit) **** SW Build 2188600 on Wed Apr 4 18:40:38...
The tb_axi_lite_xbar test is not included in the list of tests to run in scripts/run_vsim.sh
There is a combinational path in `axi_to_mem` from `axi_req_i.b_ready` to `axi_resp_o.w_ready`. In particular, this is can be dangerous when connecting this module downstream of `axi_dw_downsize`, which has a comb path...
This is a feature request to speedup simulation and CI time. Simulations for different parameterizations of an IP could be run in parallel as independent processes.
PATRONoC is a fully homogeneous AXI-compliant NoC targeted towards high bandwidth DNN platforms.
Hi axi_cdc uses fifos that don't infer dual SRAM. Fifo is implemented using registers, and it is very slow. In my design, I had to lower fifo depth to 8...
If the AXI AW and W channels are busy, the AXI AR valid can wait forever for its AR ready signal.
The AXI Slave protocol property that BRESP does not change in value while BVALID is asserted waiting for BREADY to go high is seen to be violated. The waveform shows...
Hi I have a question about the axi_lite_from_mem module: https://github.com/pulp-platform/axi/blob/master/src/axi_lite_from_mem.sv#L176 Looks like the module uses a FIFO to track the read/write order of all incoming transactions and asserts bready and...
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication