axi_cdc fpga implementation very inefficient

[skokvermon]

Hi

axi_cdc uses fifos that don't infer dual SRAM. Fifo is implemented using registers, and it is very slow. In my design, I had to lower fifo depth to 8 words in order to be able to run at 100mhz.

fifo_v3 also don't infer SRAM, which is very problematic. I could succesfully use single and dual clock fifos from optimsoc which can infer xilinx SRAM (and probably altera too). I think it would be nice to use such fifos for axi_cdc

[omeag]

Hi sir, I've been reviewing the axi_cdc, but can't find the definitions for cdc_fifo_gray_src and cdc_fifo_gray_dst modules. Could you kindly point me to where I can find them?

[micprog]

Hi @skokvermon, Generally, our IPs are focused on ASIC designs, not FPGA, thus we have not implemented inferring SRAMs, either for the CDC FIFOs or general FIFOs. Both of these use modules of the common_cells repository: fifo_v3 and cdc_fifo_gray. The tool we use to collect dependencies and generate scripts for tools (bender) allows switching out of individual files, e.g. for FPGA synthesis. While we generally use FPGA to prototype designs we implement as ASICs and attempt to avoid significant divergence for proper testing, it may be good to have a more FPGA-targeted implementation of these IPs. Feel free to open a pull request to add these modules, I'd be happy to integrate them!