edalize
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olofk
An abstraction library for interfacing EDA tools
- added 'stdcell' arch option - added 'verilog' output format option - added 'tech_lib' option to specify .lib - updated Jinja templates
See issue https://github.com/olofk/edalize/issues/123 for background. Following the discussion on my previous PR https://github.com/olofk/edalize/pull/138, I've had a go at the alternative method of calling cocotb from edalize. It still has one...
As the first step in #115 these commits add an SDF file type, with information about the instance the file should be applied to and the corner the delays represent....
I mainly copy and pasted from the VCS backend. Happy to modify however is best. It seems to run my simple tests at least.
This PR includes and thus requires #322, #325, and #326. It simply replaces the openOCD code with openFPGALoader code, which is simpler but does require an extra board specifier
This PR includes (and thus requires) #322 Now tests both VPR and NextPNR flows for F4PGA. VPR uses Yosys the way Symbiflow did, and NextPNR uses Yosys the default way....
https://github.com/olofk/fusesoc/issues/569 Exact line causing this issue: https://github.com/olofk/edalize/blob/1e11a12c6354a02e4d6a03c20e11af95238cc739/edalize/yosys.py#L126
The SymbiFlow backend is currently a mixed bag with a yosys+nextpnr-centric flow and a yosys+vpr-centric flow with the latter being called through the symbiflow_* shell script wrappers. The drawback of...
Hi, I have question if there is a reason why there are no `vopt_options` for Modelsim available? => https://github.com/olofk/edalize/blob/master/edalize/modelsim.py#L78 Would if be straight forward to add `vopt_options` hasn't this option...
Hi there, I randomly noticed that when running fusesoc for Verilator that it uses all available CPUs for a parallel build. This seems to be due to the following lines...