edalize
edalize copied to clipboard
olofk
An abstraction library for interfacing EDA tools
Can be seen in action here: https://github.com/joennlae/halutmatmul/blob/master/hardware/halut_top.core
This is the first step in implementing #323. We created a new flow using the Edaflow system that runs the built-in Yosys/VPR tools (with some modifications). The module has been...
This is an ongoing project that @schafernc and I are working on as undergrad students under the supervision of @jgoeders. This is essentially our attempt at implementing #302 to rework...
This PR includes (and thus requires) #322 and #325 First, a minor fix adding the pnr tool option to the EDAM API page Second, a new page is created where...
The run_main runs the spyglass tool. There are two targets in the make file. args = ["-i"] option is required to ignore the error code from the first design read...
This PR adds support to Project XRay supporting Xilinx series 7 FPGAs. Currently I'm testing with Kintex 7 and a QMTech board. The work is based on https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr and is...
This is a first pass at the filelist backend. Still looking for feedback from the original discussion but thought a PR might kick start that. No test updates yet. See...
the previous state of the xcelium flow was not working correctly. I have created a new flow based on the existing flow - adding a lot more freedom for the...
I'm working on adding a back-end to run the VTR tool (https://verilogtorouting.org/)
This allow adding TCL scripts on pre-synthesize, pre-pnr and pre-bistream generation for the Libero backend. In the .core file, this would be defined like: ```yaml polarfireeval: files: - rtl/corescore_polarfire_eval_clock_gen.v: {...