Max Korbel
Max Korbel
## Motivation If modules leverage ROHD's `Interface`s and want them propagated through a `Pipeline` abstraction in ROHD, it requires the user to generate per-port connectivity through the `Pipeline` and reconstruct...
## Motivation In SystemVerilog, it's easy to index an entry in an array of signals: ```SystemVerilog logic [8:0] a [4:0]; logic b [4:0]; logic[8:0] c; assign c = a[b]; ```...
The implementation for `Mux` maps to a SystemVerilog ternary operator (`? :`). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nested `Mux`s and...
## Motivation There have been multiple bugs found related to zero-width `Logic`s and `LogicValue`s. ## Desired solution Add a bunch of tests covering behavior of things when the are zero-width,...
## Describe the bug Shift operations for large `LogicValue`s (near/at the 64-bit int max or above into BigInt territory) cause a variety of exceptions and incorrect behavior. ## To Reproduce...
## Motivation It doesn't make sense for a signal to be driven by two drivers in a `Sequential` block. The code already prevents this, but testing is incomplete. ## Desired...
## Motivation It would be nice if the generated outputs (e.g. SystemVerilog, waveform dumps) had a guaranteed accurate version number of ROHD that generated them. A version number (from pubspec.yaml)...
## Motivation Verbosity of generated SystemVerilog could be reduced by collapsing in-line assignments where the driver is equal. For example, merge these two: ```SystemVerilog assign out = {b,a}; // swizzle_0...
## Motivation It would be nice to provide a mechanism to do math on signals/values of different widths when it is unambiguous. It's also potentially useful to have a larger...
## Motivation When multiple cases match on a unique case statement, it currently causes an exception to be thrown. Perhaps this should be a configurable option allowing X's to be...