Collapse equivalent in-line assignments in the SystemVerilog synthesizer

[mkorbel1]

Motivation

Verbosity of generated SystemVerilog could be reduced by collapsing in-line assignments where the driver is equal. For example, merge these two:

assign out = {b,a};  // swizzle_0
assign out_0 = {b,a};  // swizzle

Desired solution

Add a function called something like _collapseEquivalentInlineModules to the SystemVerilog synthesizer, run similarly to _collapseChainableModules.

Alternatives considered

Abandon this idea and rely on other SystemVerilog generators like CIRCT for fancier optimization like this.

Additional details

Do not collapse non-renameable outputs directly, create a buffer signal... maybe do this before collapsing assignments, always add a buffer, then let assignment collapsing handle it? This can be easily done using existing merge capabilities for synthlogic?