Max Korbel

Maybe a function on `Logic` called `select` or something that operates on an indexable `Iterable` that automatically generates the hardware to select the right one?

Adding something like += and -= would also be good!

Needs extensive testing as well, obviously

This also needs to consider things like `toInt` and `toBigInt` for `LogicValue`. Currently, if you have a 64-bit `LogicValue`, then the resulting `toInt` is signed, but if it's less then...

Yes, I think this idea can be used to generate multi-dimensional arrays, but it will take some thought on how to implement things in a way that provides good value...

This structuring or bundling should play nicely with `Interface`s as well. For example, it would be nice to grab all of the signals in an `Interface` with a specific tag...

There's desire to use this type of solution for at least wrapping/generating SystemVerilog modules with multi-dimensional ports

There's an opportunity to provide some extra automation for sub-interface connections as well.

This is applicable to ports for modules, so need to pay close attention to both module declarations and instantiations Related bug for swizzling specifically: #122

Add tests for `Logic` by `Const` and `Const` by `Logic` as well