Create a way to make a chain of `Mux`s in a less verbose way

[mkorbel1]

The implementation for Mux maps to a SystemVerilog ternary operator (? :). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nested Muxs and lots of parentheses in ROHD. A module that supports chained mux behavior would be nice.

[mkorbel1]

It would also be nice if there's a way to construct a Mux without needing to access the output explicitly. Maybe as simple as a mux function that gets the output.