rohd
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Shift broken for large `LogicValue`s
Describe the bug
Shift operations for large LogicValue
s (near/at the 64-bit int max or above into BigInt territory) cause a variety of exceptions and incorrect behavior.
To Reproduce
Here's a couple tests that fail:
expect((LogicValue.filled(64, LogicValue.one) >> 2).toInt(),
equals(-1 >> 2));
expect(
(LogicValue.filled(65, LogicValue.one) >> 10),
equals([
LogicValue.filled(10, LogicValue.zero),
LogicValue.filled(55, LogicValue.one)
].swizzle()));
Expected behavior
No exceptions and accurate behavior.
Actual behavior
Exceptions and incorrect behavior.
Additional details
Extensive testing around this area needs to be added.
Additional context
Add any other context about the problem here.
Add tests for Logic
by Const
and Const
by Logic
as well
Hey @mkorbel1 , can please you confirm if this issue is already fixed in some other PR.
Since >>
represents arithmetic right shift (instead of >>>
as in System Verilog) as mentioned, I think code is working as required i.e.,
-1
& LogicValue.filled(64, LogicValue.one)
will always produce -1
on arithmetic right shift irrespective of number of shifts we would like to make.
Again in LogicValue.filled(65, LogicValue.one) >> 10
as per arithmetic right shift, there won’t be any change on the LogicValue since all bits were already 1 ( along with MSB). Hence, this test case must fail.
But there some interesting highly unlikely case where SystemVerilog is able to generate the results on any infinite shifts considering the number of shifts, type of shift and value need to be shifted, E.g. -1 >> (+inf), 0 >> (+inf) , 1<<(+inf)
works fine, but rohd & dart will throw error.
Please let me know If I misunderstood anything.
@Sanchit-kumar sorry for the late response on this, somehow I missed your comment! PR #412 fixes the issues here. You're right regarding the typo in the example test in this issue. There's no "infinity" to worry about in Dart, but the fixes will handle arbitrarily large shift amounts properly now