Tim 'mithro' Ansell
Tim 'mithro' Ansell
These examples are from [Verilog — 2001 - A Guide to the New Features of the Verilog® Hardware Description Language](https://link.springer.com/book/10.1007/978-1-4615-1713-9) Section [`25. Attributes`](https://link.springer.com/chapter/10.1007%2F978-1-4615-1713-9_27), ```verilog always @(state) //state machine with one-hot...
@kgugala
@litghost - Upstream Yosys only has the ability to ignore attributes on parameters? This is full attribute on parameters support with tests...
Should the timing information be provided by the black box implementation rather than vpr?
@kgugala / @acomodi
@tpagarani - Not opposed to seeing this happening, just wondering if that is a work around or solution which results in less duplication in the output?
Can the lookahead be generated once and then saved / loaded?
How big is the file, could it just be shipped with the interchange files in some way?
@umarcor This would be great to add!
@daniellimws -- Look at this! It is super awesome!