Tim 'mithro' Ansell comments

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                                            Tim 'mithro' Ansell

Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?)

So I think this bug report has gotten a bit off topic here. Can we loop back to just the idea around the question; > Should Migen generate explicit Verilog...

Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?)

From the counting page you linked too, it says; > The convertor will generate the required sign extensions, resizings and type castings. It therefore automates this tedious and error-prone bookkeeping...

Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?)

Just FYI - @cliffordwolf [has a tool called vloghammer](http://www.clifford.at/yosys/vloghammer.html) which he uses to find bugs in various Verilog implementations.

Add VexRISCV configuration suitable for iCE40 sized devices

Yes, LiteX uses wishbone internally if I understand correctly. A small 1k or 4k instruction cache might still make sense, even on an ice40?

Add VexRISCV configuration suitable for iCE40 sized devices

Btw would you like me to send you some iCE40 hardware like the TinyFPGA BX?

Create a "spi settings" type thing (in same vein as the SDRAM settings)

We have been using a hack like this; * https://github.com/mithro/HDMI2USB-litex-firmware/blob/nextgen/platforms/atlys.py#L619 * https://github.com/mithro/HDMI2USB-litex-firmware/blob/nextgen/platforms/mimasv2.py#L121 * https://github.com/mithro/HDMI2USB-litex-firmware/blob/nextgen/platforms/minispartan6.py#L159 OpenOCD has a pretty nice table at http://repo.or.cz/openocd.git/blob/HEAD:/src/flash/nor/spi.c#l32

Create a "spi settings" type thing (in same vein as the SDRAM settings)

These seem to be the settings needed? ```python spiflash_read_dummy_bits = 8 spiflash_clock_div = 4 spiflash_total_size = int((16/8)*1024*1024) # 16Mbit spiflash_page_size = 256 spiflash_sector_size = 0x10000 ```

redesign platform resource

This is something I'm interested in. I've already started playing with a classed based approach at https://github.com/mithro/HDMI2USB-litex-firmware-old/blob/pmod-extra/pmod.py

redesign platform resource

Oh, there is also some stuff for my ["TOFE" standard](https://tofe.io) in the [HDMI2USB-litex-firmware repo](https://github.com/timvideos/HDMI2USB-litex-firmware). See https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/platforms/tofe_axiom.py and https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/platforms/tofe_lowspeedio.py This is then used in * https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/gateware/tofe.py * https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/opsis/base.py#L289-L293 * https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/opsis/axiom.py This...

Output better error message for flash_proxy.

Done, but I wasn't really sure how to test I didn't break things?